In a process of developing and manufacturing a semiconductor device, the semiconductor device is evaluated by measuring a PN junction capacitance between a well of a first conductive type and a diffusion layer of a second conductive type in the semiconductor device. Here, a case where a conventional technique described in Japanese Patent Publication (JP-A-Heisei 9-74122: patent literature 1) is applied to measurement of a capacitance of a semiconductor device will be described. In this case, two kinds of measurement patterns of a DUT (Device Under Test) pattern semiconductor device and a calibration pattern semiconductor device are used.
FIG. 1A shows a plan view of the DUT pattern semiconductor device, and FIG. 1B is a diagram showing a sectional of the semiconductor device along on a line X-X′ of FIG. 1A and a semiconductor device measuring system applied to the DUT pattern semiconductor device.
The DUT pattern semiconductor device includes a semiconductor substrate 400 of a first conductive type; a well 406 of a second conductive type; insulating films 405-1 to 405-3; a diffusion layer 407 of the first conductive type; a diffusion layer 408 of the second conductive type; an insulating film 413; via-contacts 403-1, 403-2; first-layer metal wiring layers 401-1 and 401-2; an insulating film 414; via-contacts 404-1 and 404-2; and second-layer metal wiring layers 402-1 and 402-2. Here, the first conductive type and the second conductive type are assumed to be an N-type and a P-type, respectively.
The semiconductor substrate 400 of the N-type has the well 406 of the P-type formed on the surface portion thereof. The well 406 of the P-type has the insulating films 405-1 to 405-3 formed in its surface portion thereof. The diffusion layer 407 of the N-type is formed between the insulating film 405-1 and the insulating film 405-2 in the surface portion of the well 406 of the P-type. The diffusion layer 408 of the P-type is formed between the insulating film 405-2 and the insulating film 405-3 in the surface portion of well 406 of the P-type. The well 406 of the P-type, the insulating films 405-1 to 405-3, the diffusion layer 407 of the N-type, and the diffusion layer 408 of the P-type are covered with the insulating film 413. The via-contact 403-1 is formed on the diffusion layer 407 of the N-type to pass through the insulating film 413. The via-contact 403-2 is formed on the diffusion layer 408 of the P-type to pass through the insulating film 413. The first-layer metal wiring layers 401-1 and 401-2 are formed on the via-contacts 403-1 and 403-2, respectively.
The first-layer meal wiring layers 401-1 and 401-2 are covered with the insulating film 414. The via-contacts 404-1 are formed on the first-layer meal wiring layer 401-1 to pass through the insulating film 414. The via-contacts 404-2 are formed on the first-layer meal wiring layer 401-2 to pass through the insulating film 414. The second-layer metal wiring layers 402-1 and 402-2 are formed on the via-contacts 404-1 and 404-2, respectively.
An LCR meter is usually used for measurement of the DUT pattern semiconductor device. The LCR meter 410 has a power supply and an ammeter. The power supply is connected between a ground terminal GND grounded and a high-voltage terminal High for supplying a first voltage. The ammeter is connected between a low-voltage terminal Low for supplying a second voltage lower than the first voltage, and the ground terminal GND. In the LCR meter 410, a voltage, in which a small AC voltage is superimposed on a DC bias voltage, is applied between the high voltage terminal High and the low voltage terminal Low from the power supply to a target member, and an AC current (absolute value and phase) is measured by the ammeter. Thus, the capacitance of the target member (the PN junction capacitance in this example) is calculated.
The low voltage terminal Low and the high voltage terminal High of the LCR meter 410 are respectively connected to the second-layer metal wiring layers 402-1 and 402-2 so as to measure the PN junction capacitance 409 between the diffusion layer 407 of the N-type and the well 406 of the P-type by this LCR meter 410.
There are two parasitic capacitances to be removed from the measurement in the DUT pattern semiconductor device: a parasitic capacitance 411 formed between the first-layer metal wiring layer 401-1 and the well 406 of the P-type; and a parasitic capacitance 412 formed between the first-layer metal wiring layer 401-2 and the well 406 of the P-type.
Next, an operation of a conventional semiconductor device measuring system will be described. The voltage in which a small AC voltage is superimposed on a DC bias voltage is applied to the second-layer metal wiring layer 402-2 from the high voltage terminal High of the LCR meter 410. At this time, a charging/discharging current due to the PN junction capacitance 409 flows from the high voltage terminal High to the second-layer metal wiring layer 402-2, the via-contacts 404-2, the first-layer metal wiring layer 401-2, the via-contact 403-2, the diffusion layer 408 of the P-type, the well 406 of the P-type, the PN junction capacitance 409, the diffusion layer 407 of the N-type, the via-contact 403-1, the first-layer metal wiring layer 401-1, the via-contacts 404-1, the second-layer metal wiring layer 402-1, and the low voltage terminal Low.
At the same time, a charging/discharging current due to the parasitic capacitance 411 flows from the high voltage terminal High to the second-layer metal wiring layer 402-2, the via-contacts 404-2, the first-layer metal wiring layer 401-2, the via-contact 403-2, the diffusion layer 408 of the P-type, the well 406 of the P-type, the parasitic capacitance 411, the first-layer metal wiring layer 401-1, the via-contacts 404-1, the second-layer metal wiring layer 402-1, and the low voltage terminal Low. Both ends of the parasitic capacitance 412 are electrically short-circuited by the first-layer metal wiring layer 401-2, the via-contact 403-2, the diffusion layer 408 of the P-type, and the well 406 of the P-type. Thus, the charging/discharging current by the parasitic capacitance 412 does not flow.
Here, the charging/discharging current due to the parasitic capacitance 411 flows to the low voltage terminal Low of the LCR meter 410, so that the value of the parasitic capacitance 411 is included in the measured value of the LCR meter 410. In this case, a total value of the PN junction capacitance 409 and the parasitic capacitance 411 is measured as the measured value of the LCR meter 410.
FIG. 2A shows a plan view of the calibration pattern semiconductor device. FIG. 2B is a diagram showing the section of the semiconductor device along a line X-X′ of FIG. 2A and the semiconductor device measuring system applied to the calibration pattern semiconductor device. In the calibration pattern semiconductor device, the via-contact 403-1 is removed from the DUT pattern semiconductor device.
In the calibration pattern semiconductor device, because there is not the via-contact 403-1, the charging/discharging current due to the PN junction capacitance 409 does not flow but only the charging/discharging current due to the parasitic capacitance 411 flows through the LCR 410. In this case, the parasitic capacitance 411 is measured as the measured value of the LCR meter 410.
In this manner, in the conventional semiconductor device measuring system, the value of only the PN junction capacitance 409 can be obtained by subtracting the measured value of the calibration pattern semiconductor device from the measured value of the DUT pattern semiconductor device.